The amount of data transferred between devices in computer systems has been increasing at a tremendous pace that shows no signs of abating. In particular, the amount of data transferred between memory devices and other devices, such as devices implemented using field programmable gate arrays (FPGAs), has grown prodigiously. Unfortunately, the rate at which these devices can process data has increased faster than the memory device's capacity to provide it. For this reason, faster memory interface protocols are being developed.
One such faster protocol is the Double-Data Rate 3 (DDR3) interface standard. In this standard, several memory devices communicate with a memory interface circuit on an FPGA or other device. Each memory device communicates using a number of data or DQ signals and a strobe or DQS signal. While the FPGA receives data, the FPGA provides a system clock signal to the memory devices, each of which provide a DQS and a number of DQ signals to the memory interface circuit. The memory devices use the system clock to adjust the frequency of the DQS and DQ signals. However, the system clock is routed to the memory devices using a fly-by topology. Accordingly, the DQ and DQS signals are provided asynchronously to the memory interface, that is, each memory device may provide DQS and DQ signals having any phase relationship to the system clock.
The DQ signals received by the memory interface are retimed using a phase-shifted version of the corresponding DQS signals. These retimed signals need to be retimed once again to an internal clock, which may be the system clock or a second clock signal, to transfer the signals to the core of the device. Unfortunately, if the timing between the phase-shifted DQS signal and the system clock is not optimal, data recovery errors may result. Conventional techniques have included using first-in-first-out memories, but these are comparatively large, complex circuits.
Thus, what is needed are circuits, methods, and apparatus that provide for the efficient transfer of data from a device's inputs to its core circuitry.